1. Technical Field
Methods of manufacturing flash memory cells, and more particularly to, methods of forming a self-aligned floating gate capable of increasing the coupling ratio of flash memory cells are disclosed.
2. Description of the Related Art
Generally, a flash memory cell is implemented using a shallow trench isolation (STI) process as a device isolation process. During the process of isolating a floating gate using mask patterning, wafer uniformity is very poor depending on variation in a mask critical dimension (CD). It is thus difficult to implement a uniform floating gate. Further, there are problems such as program and erase fail of the memory cell, or the like, depending on variation in the coupling ratio.
In addition, in a higher-integrated design, when a space of below 0.13 μm is implemented, the masking process is difficult. Thus, a process of manufacturing the flash memory cell serving as an important factor in implementing a uniform floating gate becomes further difficult. Also, if the floating gate is not uniformly formed, difference in the coupling ratio becomes severe. Thus, upon program and erase of the memory cell, there is a possibility that the memory cell may be over erased. This adversely affects a device characteristic. Also, the yield of the product is lowered and the cost is increased, due to increase in the mask process.